ASIC Design: What Is ASIC Design? | System To ASIC (2023)

In this article, we’ll go over the ASIC design modeling process, gate-level physical design, and its specifications.

Table Of Contents

  1. What Is ASIC Design
  2. ASIC Specification
  3. Logic Design
  4. Physical Design
  5. Additional Resources

What Is ASIC Design?

ASIC design is a methodology of cost and size reduction of an electronic circuit, product or system through miniaturization and integration of individual components and their functionality into a single element – an Application Specific Integrated Circuit (ASIC).

An electronic product commonly consists of many integrated circuits (ICs) which are interconnected together to perform a particular function. For example, a 1980’s smoke detector was built entirely of general-purpose ICs, such as amplifiers, comparators, regulators and discrete components such as resistors and capacitors.

It was expensive (component cost and assembly cost) and bulky (all those components required space). As competition intensified, the requirement for lower cost and smaller size drove the need for consolidation and integration of all those individual components into a single ASIC, reducing not only overall cost and size of the smoke detector but also improving its reliability (fewer parts, fewer things to go wrong).

Recently, VLSI CMOS has played a crucial role in placing millions of transistors on a single chip, providing digital system designers with an ability to implement a vast number of gates with complex functionality on a single IC.

ASIC Design: What Is ASIC Design? | System To ASIC (1)

(Video) What is an ASIC?

According to Moore’s Law, the number of gates or transistors doubles after every 18 months and is growing to extremely high densities per IC. Rapidly growing technology in logic, parallelization, CAD tools, and memory promises continued advancement in the next 15 years. With the help of CAD tools, high-level descriptions can be translated into specific functions such as registers, microcontrollers, ALU, control units and more.

ASIC Design: What Is ASIC Design? | System To ASIC (2)

Modern ASICs combine multiple complex blocks in a single package, including analog elements such as an amplifier, ADC, PLL and digital elements such as a microcontroller, OTP, ROM, EEPROM, RAM, and other building blocks. These types of ICs are known as system on chip (SoC). The analog section of the ASIC is designed using primarily transistor-level design techniques and manual layout processes. The digital section of the chip is designed primarily using hardware description languages such as VHDL/Verilog followed by automated Place and Route (PnR) layout process.

There are three types of ASIC chip designs:

  • Full Custom Design
  • Semi-Custom Design
  • Programmable ASIC

Some examples of ASIC chips include chips in the consumer, medical, automotive, and industrial sectors. ICs that are not ASICs are general-purpose ICs such as voltage regulators, stand-alone memories (EEPROM, RAM)

Feature size (μm)0.350.
DRAM bits/chip64M256M1G4G16G64G
Number of I/O90013502000260036004800
Chip-to-board speed150200250300375475
Maximum number of wiring levels (logic)4-555-666-77-8
On-chip speed (MHz)30045060080010001100

The evolution of VLSI as told by the Semiconductor Industries Association

What Is A Specification?

An ASIC specification is a document that lists how a device needs to function and perform in various operational situations such as tithe specification phase is an extremely significant part of the design and development process. As technology becomes more advanced and entrenched in every aspect of life, customers are expecting new features and design improvements from their devices, including high-speed processing and low power consumption. A top-down design approach is employed to navigate and manage complexities of the ASIC design process, and as a first step, dictates the development of a proper detailed specification. A thoroughly crafted working specification helps guide the design process, with the project less prone to errors disruptive to project schedule and cost.

(Video) ASIC Design Flow | How a chip is designed??

It is very important that an expert in ASIC system design assists customers in developing system architecture and specifications. This extensive process takes around 2 to 6 weeks depending upon the complexity of the application requirements. The specification process is followed by:

  1. Reviewing the block diagram, system schematics, and specifications
  2. Developing an understanding related to design problems, operating environment, and challenges
  3. Making a decision related to the final product, not only ASICs
  4. Determining if any certification is required in the product such as IEC, TS compliance
  5. Designing or compiling the ASIC block diagram with full functional components, specifications, and pinout
  6. Deciding board-level architectural trade-offs that lead to the most cost-effective silicon integration

What Is Logic Design?

Logic design for an ASIC begins with the design team analyzing the functional specification in order to define and create a logic design architecture. The architecture definition includes a block diagram that provides details about functional relationships between digital logic such as, finite state machines, combinational logic, sequential logic, processors, memories, data path design, communication buses, and the connections between them.

Once the architecture definition is in place, the next step is to describe detailed functionality of the blocks and connection between the respective functional blocks. Description of logic design functionality is accomplished using either a graphical depiction (schematic), or more commonly, and particularly with large systems, a purpose-specific hardware definition language (HDL code) such as Verilog and VHDL.

HDL code can be written at different levels of abstraction from transistor level logic depending on the chosen design flow and development needs. Very large systems and or complicated systems will start at the behavioral level. Behavioral is the highest level of abstraction from a gate to gate-level description and is often coded in languages such as System Verilog, Verilog, VHDL, and C. Behavioral level coding generally cannot be directly synthesized to gate-level logic but is useful for modeling and verification.

Register-Transfer Level (RTL) coding is abstracted from a gate-level description for increased coding efficiency but is synthesizable with EDA (Electronic Design Automation) tools to produce gate level and ultimately transistor-level implementations. RTL code describes the desired hardware by implying logic, by defining flip-flops, latches, and how data is transferred between them. Synthesis of RTL code utilizes the power of advanced EDA tool capabilities to, create, alter, and optimize the logic used for implementation, but not functional behavior.

Gate level coding is the least abstracted from transistor level logic. Gate level coding describes the design using the base logic gates, NAND, NOR, AND, OR, MUX, FLIP-FLOP. It does not need to be synthesized and has the lowest level of abstraction. Gate level coding is useful for smaller less complicated designs or designs that require very specific implementation for performance but does not offer the design efficiency that comes with higher levels of abstraction in concert with sophisticated EDA (Electronic Design Automation) tools.

The design team will also provide an estimate of the on-die block area required for implementation, and other details affecting the cost and power usage of the digital logic system.

(Video) STA in ASIC design flow | Accuracy of STA


The logical design is verified for matching of original design intent and implementation at several stages throughout the design process to ensure an accurate successful ASIC outcome. The verification process includes applying test cases to the detailed design description and confirming that the expected behavior is achieved. Verification is also carried out at additional stages of the design, using sophisticated EDA tools to compare gate-level netlists to the design description and actual layout implementation to the synthesized netlist. If any verification test fails along the way, the design is sent back for correction to the design department responsible for that particular part of the implementation. Continual design and implementation verification throughout the development process catch errors and design deficiencies before they become costly time-consuming mistakes.

Design Synthesis

Design synthesis is the process of translating the logical design into a gate-level netlist that can then be implemented as a physical silicon structure. The logical design and its detailed description are technology-independent until the synthesis process. The synthesis process uses advanced EDA tools that are aware of the capabilities and limitations of the target technology (FAB process) that the high-level abstracted design is being ported to. Design synthesis output is technology-dependent, tailored to the target ASIC process.

ASIC Design: What Is ASIC Design? | System To ASIC (3)

Image Courtesy of Wikimedia Commons

What Is Physical Design?

Physical design (also known as back-end design) is the process of converting the gate-level netlist produced at synthesis into functional ASIC hardware. Physical design steps include floor planning, power planning, partitioning, placement, routing, clock tree synthesis, final verification, and export as a GDSII file to the fabrication facility for construction. A number of high-level EDA tools from various vendors such as Cadence, Synopsis, Magma, Mentor Graphics are available to facilitate back-end design. They each have their strengths and weaknesses and are sometimes used in concert to achieve an efficient implementation path with optimal results.


Floorplanning is the process of placing functional blocks in the chip area so as to allocate routing areas between them, plan for critical power and ground connections, and determine Input / Output (IO) pad locations. A good floorplan will balance design constraints to minimize total die area, optimize signal routing channels for ease of layout and signal performance, and relative placement of functional blocks to minimize interference and preserve signal integrity. Careful floorplanning is key to how well the rest of the physical design process flows.


Partitioning (logical partitioning) is the process of dividing the chip into small blocks. The objective of partitioning is to make the functional block easier for placement and routing. This step can be done in the logical design phase when the design team divides the entire design into sub-blocks for development, or at the physical design (back-end) phase to aid in place and route activities focused on routing channels, signal integrity, and dies utilization.

(Video) ASIC Design Flow | RTL to GDS | Chip Design Flow

Power Planning

Power planning takes into account the energy usage of each block, individual voltage supplies, ground paths, and interaction between them. Power Planning is one of the most important stages in Physical design. It is actually an integral part of the floorplanning process, but due to its significance in ASIC performance and function, it is often addressed as a separate stage of consideration.

During power planning, location for ground and power rings, cross die trunks, and isolated routes for sensitive circuits are allocated. Constraints for internal core ASIC circuitry and I/O cell power management are treated separately because they often have different demands. Special power pads are used for positive supply, ground, and negative supply. Multiple power and ground pads are often used to reduce the series resistivity and inductive impedance that affects, voltage drop, signal integrity, and high-speed performance.


Placement is the process of dividing the chip into smaller blocks by placing the correct position to standard cells with none overlapping on the chip. Placement is performed in four optimization phases: pre-placement, in-placement, and post-placement before and after clock tree synthesis.

Clock Tree Synthesis

ASIC Design: What Is ASIC Design? | System To ASIC (4)

Clock tree synthesis is the process of ensuring that clock signals are distributed evenly to all sequential elements in a design with the primary objective of preventing clock timing-related errors. Clocking of gates in high-speed designs are subject errors as a result of the clock edge not arriving at the exact time it is expected relative to when it arrived at other parts of the circuit. This timing error is called clock skew and is dependant on a number of variables both in the original design and in physical implementation.

Clock tree synthesis performed during the physical design process considers the effects of place and route, channel impedance, parasitic loads, etc. Then through the insertion of buffers or inverters along the clock paths to minimize or balance skew of important clock signal chains, build a clock tree that achieves proper timing across the entire design.


Routing is the process of connecting macros, standard cells, I/O ports, power, and the clock physically with metal traces. Routing is divided into two steps: global and detailed routing. In global routing, trace or wire length, and route channel congestion are estimated. In detailed routing, the actual connections within each block are made.

(Video) ASIC in VLSI Design || Types of ASIC


Design For Manufacture is paramount to achieve production yield and part reliability. As ASIC designs become larger and more complex and process technologies become more intricate, it is important that key factors such as process limitations, parameter repeatability, environmental and signal stresses are considered and factored to increase the probability of successful part to part results. Factoring of process and use constraints to increase yield, decrease test time, and other processing concerns are what is termed design-for-manufacture (DFM). DFM can often be the difference between a successful ASIC project that meets cost, reliability, and production goals versus one that falls short.

Additional Resources


What is the ASIC design? ›

ASIC design is a methodology of cost and size reduction of an electronic circuit, product or system through miniaturization and integration of individual components and their functionality into a single element – an Application Specific Integrated Circuit (ASIC).

What is ASIC design and explain all types of ASICs? ›

As the name indicates, ASIC is a non- standard integrated circuit that is designed for a specific use or application. • Generally an ASIC design will be undertaken for a product that will have a large production run , and the ASIC may contain a very large part of the electronics needed on a single integrated circuit.

What is ASIC design in VLSI? ›

ASIC in VLSI stands for application-specific integrated circuit. This integrated circuit is aptly named since an ASIC microchip is designed and manufactured for one specific application and does not allow you to reprogram or modify it after it is produced. This means ASICs are not intended for general use.

What is the full form of ASIC? ›

The name ASIC means application-specific integrated circuit, meaning that the internal circuits are designed and connected up to carry out one specific task for a single company in a specific application.

What are the two types of ASICs? ›

There are three different types of ASICs: red, grey and white. The type of ASIC you require will depend on your role and operational need.

Why do we use ASIC? ›

From electronic toys, cell phones, and digital watches to communications satellites, avionics, and A.I. programs, the custom programming, compact size, and high reliability of ASIC chips make it a popular choice for industry, intelligence agencies, space programs, and defense systems.

What are the 3 categories of ASIC? ›

Gate Array Based ASIC are of three types. They are Channeled Gate Array, Channel less gate array and a structured gate array.

How does an ASIC work? ›

An application-specific integrated circuit (ASIC) is generally optimized to compute just a single function or set of related functions. Bitcoin miners review and verify previous bitcoin transactions and create new blocks to add the data to the blockchain.

What is ASIC example? ›

An application-specific integrated circuit (ASIC /ˈeɪsɪk/) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use. For example, a chip designed to run in a digital voice recorder or a high-efficiency video codec (e.g. AMD VCE) is an ASIC.

What is difference between ASIC and SOC? ›

ASICs are chip that is basically hardwired to do a specific job. It is not something that can be used for some general-purpose application. SOC → System on Chip. It is basically a cluster / collection or group of different types of processor components like CPU/GPU/Modems/DSP units and memory units.

Which language is used in ASIC? ›

The logic function of ASIC is specified in a similar way as in the case of FPGAs, using hardware description languages such as Verilog or VHDL.

What is ASIC made of? ›

ASICs are made from a wafer which is produced using the Czochralski process where extremely pure silicon is grown into mono-crystalline cylindrical ingots. The ingots or boules are grown up to 300 mm in diameter.

Where is ASIC based? ›

ASIC has an office in Sydney which handles enforcement and policy issues.

How many ASICs are there? ›

As we know, one million is equal to 10 lakhs, then one lakh is equal to 0.1 million. For example, 5 lakhs to million is equal to: 5 x 0.1 = 0.5 Million.
Lakhs to Million Conversion Table.
500 Lakhs50 Million
1000 Lakhs100 Million
10000 Lakhs1000 Million
7 more rows

Are ASICs digital or analog? ›

“It is only economical to integrate analog functions into an ASIC if the analog content is minimal.” The ASIC concept began as an integration strategy for lowering the costs of computationally heavy logic circuits. Today after more than three decades in use, ASICs remain heavily digitally oriented.

What do ASIC designers do? ›

As an ASIC Design Engineer, the individual's primary responsibility will be RTL design. This will include block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs.

Is ASIC effective? ›

Overall, ASIC have been successful, or partly successful, in 88% of civil litigation enforcement actions it undertakes in the Federal Court (including the full court) and the High Court*.

What can you do with an ASIC? ›

  • Financial advice. Reportable situations for AFS and credit licensees.
  • Managed funds. Managed investment schemes. Applying for relief from the financial services provisions that apply to schemes. Corporate collective investment vehicles. Managed discretionary accounts. Platforms. Exchange traded products.
30 Mar 2021

Who needs an ASIC? ›

The ASIC key is used for business names, self-managed superannuation fund (SMSF) auditors and Australian financial services (AFS) licensees. If you want to update your company details or log in with your corporate key, you need to use your corporate key.

Is an ASIC a processor? ›

(Application Specific Integrated Circuit) Pronounced "A sik," an ASIC is a chip that is custom designed for a specific purpose. Although CPUs and microcontrollers (MCUs) are also custom designed, they fall under the "general purpose" processor category. See CPU, microcontroller and ASIC miner.

What powers does ASIC have? ›

ASIC's regulatory powers

We regulate Australian corporations, financial markets, and financial services organisations and professionals who deal and advise in investments, superannuation, insurance, deposit taking and credit. We regulate these entities under a number of Commonwealth laws.

Who runs ASIC? ›

Joseph Longo commenced as ASIC Chair on 1 June 2021. He has more than 38 years experience in corporate law, financial services, governance and regulation in Australia and overseas.

How is ASIC verification done? ›

In order to verify the chip, engineers can use various tools, ranging from pre-developed simulation models and emulation to the ASIC test chip and FPGA. With emulation, for instance, they can verify designs using real hardware or can use interfaces with real HW components.

How does a ASIC work? ›

An ASIC miner is a computerized device that uses ASICs for the sole purpose of "mining" digital currency. Generally, each ASIC miner is constructed to mine a specific digital currency. So, a Bitcoin ASIC miner can mine only bitcoin.

How is an ASIC built? ›

ASICs are made from a wafer which is produced using the Czochralski process where extremely pure silicon is grown into mono-crystalline cylindrical ingots. The ingots or boules are grown up to 300 mm in diameter.

Where is ASIC based? ›

ASIC has an office in Sydney which handles enforcement and policy issues.

What is inside an ASIC? ›

Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip).

What are ASIC machines? ›

Application-specific integrated circuit (ASIC) miners are computers that are designed specifically to mine cryptocurrency. Though any cryptocurrency that operates using proof of work can be mined using ASIC miners, they're generally used for Bitcoin mining.

Does ASIC have software? ›

ASIC is a compiler and integrated development environment for a subset of the BASIC programming language. It was released for MS-DOS and compatible systems as shareware. Written by Dave Visti of 80/20 Software, it was one of the few BASIC compilers legally available for download from BBSes.

Is an ASIC a processor? ›

(Application Specific Integrated Circuit) Pronounced "A sik," an ASIC is a chip that is custom designed for a specific purpose. Although CPUs and microcontrollers (MCUs) are also custom designed, they fall under the "general purpose" processor category. See CPU, microcontroller and ASIC miner.

Who manufactures ASIC? ›

(Samsung Group), ON Semiconductor Corporation, Xilinx, Inc., Taiwan Semiconductor Manufacturing Company Limited (TSMC), Intel Corporation, Infineon Technologies AG, Bitmain Technologies Holding Company, Nvidia Corporation, and Texas Instruments, Inc.


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